High-Bandwidth, Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

This article presents an integrated current mode configurable analog block (CAB) system for field-programmable array (FPAA). The proposed architecture is based on the complementary metal-oxide semiconductor (CMOS) transistor level design where MOSFET transistors operating in saturation region are adopted. CAB designed to implement six of widely used operations processing systems: addition, subtraction, integration, multiplication, division, and pass operation. functionality demonstrated through these operations, each operation chosen user’s selection interface system. proposes optimized way designing integrating only three functional cells with circuitry achieve operations. Furthermore, programming digital tuning implemented control cells. Moreover, circuitries play essential role optimizing performance design. Simulation CMOS Transistor Based carried out using Tanner EDA Tools 0.35 μm standard technology. uses a V power supply results maximum 3 dB bandwidth 34.9 MHz approximate size 0.0537 . demonstrates advantages over state-of-the-art designs presented comparison this article. Consequently, has clear aspect simplicity, low consumption, high operation, which makes it suitable candidate mobile telecommunications applications.